This design is targeted for xczu19eg board (part number: xczu19eg-ffvb1517-2-i)

Zynq UltraScale+ Design Summary

Device	xczu19eg
SpeedGrade	-2
Part	xczu19eg-ffvb1517-2-i
Description	Zynq UltraScale+ PS Configuration Report
Vendor	Xilinx

MIO Table View

MIO Pin	Peripheral	Signal	IO Type	Speed	Pullup	Direction	Drive Strength(mA)
MIO 0	Quad SPI Flash	sclk_out	cmos	slow	pullup	out	12
MIO 1	Quad SPI Flash	miso_mo1	schmitt	slow	pullup	inout	12
MIO 2	Quad SPI Flash	mo2	schmitt	slow	pullup	inout	12
MIO 3	Quad SPI Flash	mo3	schmitt	slow	pullup	inout	12
MIO 4	Quad SPI Flash	mosi_mi0	schmitt	slow	pullup	inout	12
MIO 5	Quad SPI Flash	n_ss_out	cmos	slow	pullup	out	12
MIO 6	GPIO0 MIO	gpio0[6]	schmitt	slow	pullup	inout	12
MIO 7	GPIO0 MIO	gpio0[7]	schmitt	slow	pullup	inout	12
MIO 8	GPIO0 MIO	gpio0[8]	cmos	slow	pullup	inout	12
MIO 9	GPIO0 MIO	gpio0[9]	schmitt	fast	pullup	inout	12
MIO 10	GPIO0 MIO	gpio0[10]	schmitt	slow	pulldown	inout	12
MIO 11	GPIO0 MIO	gpio0[11]	schmitt	slow	pulldown	inout	12
MIO 12	NAND	nfc_dqs_out	schmitt	slow	pullup	inout	12
MIO 13	NAND	nfc_ce[0]	cmos	slow	pullup	out	12
MIO 14	NAND	nfc_cle	cmos	slow	pullup	out	12
MIO 15	NAND	nfc_ale	cmos	slow	pullup	out	12
MIO 16	NAND	nfc_dq_out[0]	schmitt	slow	pullup	inout	12
MIO 17	NAND	nfc_dq_out[1]	schmitt	slow	pullup	inout	12
MIO 18	NAND	nfc_dq_out[2]	schmitt	slow	pullup	inout	12
MIO 19	NAND	nfc_dq_out[3]	schmitt	slow	pullup	inout	12
MIO 20	NAND	nfc_dq_out[4]	schmitt	slow	pullup	inout	12
MIO 21	NAND	nfc_dq_out[5]	schmitt	slow	pullup	inout	12
MIO 22	NAND	nfc_we_b	cmos	slow	pullup	out	12
MIO 23	NAND	nfc_dq_out[6]	schmitt	slow	pullup	inout	12
MIO 24	NAND	nfc_dq_out[7]	schmitt	slow	pullup	inout	12
MIO 25	NAND	nfc_re_n	cmos	slow	pullup	out	12
MIO 26	GPIO1 MIO	gpio1[26]	schmitt	slow	pullup	inout	12
MIO 27	NAND	nfc_rb_n[0]	schmitt	fast	pullup	in	12
MIO 28	GPIO1 MIO	gpio1[28]	schmitt	slow	pullup	inout	12
MIO 29	GPIO1 MIO	gpio1[29]	cmos	slow	pullup	inout	12
MIO 30	GPIO1 MIO	gpio1[30]	schmitt	slow	pullup	inout	12
MIO 31	GPIO1 MIO	gpio1[31]	schmitt	slow	pullup	inout	12
MIO 32	UART 1	txd	cmos	slow	pullup	out	12
MIO 33	UART 1	rxd	schmitt	fast	pullup	in	12
MIO 34	GPIO1 MIO	gpio1[34]	cmos	slow	pullup	inout	12
MIO 35	GPIO1 MIO	gpio1[35]	schmitt	fast	pullup	inout	12
MIO 36	GPIO1 MIO	gpio1[36]	cmos	slow	pullup	inout	12
MIO 37	GPIO1 MIO	gpio1[37]	schmitt	fast	pullup	inout	12
MIO 38	SD 0	sdio0_clk_out	cmos	slow	pullup	out	12
MIO 39	GPIO1 MIO	gpio1[39]	schmitt	slow	pullup	inout	12
MIO 40	SD 0	sdio0_cmd_out	schmitt	slow	pullup	inout	12
MIO 41	SD 0	sdio0_data_out[0]	schmitt	slow	pullup	inout	12
MIO 42	SD 0	sdio0_data_out[1]	schmitt	slow	pullup	inout	12
MIO 43	SD 0	sdio0_data_out[2]	schmitt	slow	pullup	inout	12
MIO 44	SD 0	sdio0_data_out[3]	schmitt	slow	pullup	inout	12
MIO 45	SD 1	sdio1_cd_n	schmitt	fast	pullup	in	12
MIO 46	SD 1	sdio1_data_out[0]	schmitt	slow	pullup	inout	12
MIO 47	SD 1	sdio1_data_out[1]	schmitt	slow	pullup	inout	12
MIO 48	SD 1	sdio1_data_out[2]	schmitt	slow	pullup	inout	12
MIO 49	SD 1	sdio1_data_out[3]	schmitt	slow	pullup	inout	12
MIO 50	SD 1	sdio1_cmd_out	schmitt	slow	pullup	inout	12
MIO 51	SD 1	sdio1_clk_out	cmos	slow	pullup	out	12
MIO 52	Gem 2	rgmii_tx_clk	cmos	slow	pullup	out	12
MIO 53	Gem 2	rgmii_txd[0]	cmos	slow	pullup	out	12
MIO 54	Gem 2	rgmii_txd[1]	cmos	slow	pullup	out	12
MIO 55	Gem 2	rgmii_txd[2]	cmos	slow	pullup	out	12
MIO 56	Gem 2	rgmii_txd[3]	cmos	slow	pullup	out	12
MIO 57	Gem 2	rgmii_tx_ctl	cmos	slow	pullup	out	12
MIO 58	Gem 2	rgmii_rx_clk	schmitt	fast	pullup	in	12
MIO 59	Gem 2	rgmii_rxd[0]	schmitt	fast	pullup	in	12
MIO 60	Gem 2	rgmii_rxd[1]	schmitt	fast	pullup	in	12
MIO 61	Gem 2	rgmii_rxd[2]	schmitt	fast	pullup	in	12
MIO 62	Gem 2	rgmii_rxd[3]	schmitt	fast	pullup	in	12
MIO 63	Gem 2	rgmii_rx_ctl	schmitt	fast	pullup	in	12
MIO 64	USB 1	ulpi_clk_in	schmitt	fast	pullup	in	12
MIO 65	USB 1	ulpi_dir	schmitt	fast	pullup	in	12
MIO 66	USB 1	ulpi_tx_data[2]	schmitt	slow	pullup	inout	12
MIO 67	USB 1	ulpi_nxt	schmitt	fast	pullup	in	12
MIO 68	USB 1	ulpi_tx_data[0]	schmitt	slow	pullup	inout	12
MIO 69	USB 1	ulpi_tx_data[1]	schmitt	slow	pullup	inout	12
MIO 70	USB 1	ulpi_stp	cmos	slow	pullup	out	12
MIO 71	USB 1	ulpi_tx_data[3]	schmitt	slow	pullup	inout	12
MIO 72	USB 1	ulpi_tx_data[4]	schmitt	slow	pullup	inout	12
MIO 73	USB 1	ulpi_tx_data[5]	schmitt	slow	pullup	inout	12
MIO 74	USB 1	ulpi_tx_data[6]	schmitt	slow	pullup	inout	12
MIO 75	USB 1	ulpi_tx_data[7]	schmitt	slow	pullup	inout	12
MIO 76	MDIO 2	gem2_mdc	cmos	slow	pullup	out	12
MIO 77	MDIO 2	gem2_mdio_out	schmitt	slow	pullup	inout	12

PS Clocks information

PSS REF CLK : 33.333

Name	Source	Input Frequency (MHz)
APLL	PSS_REF_CLK	2666.640
DPLL	PSS_REF_CLK	2133.312
VPLL	PSS_REF_CLK	2999.970
RPLL	PSS_REF_CLK	2133.312
IOPLL	PSS_REF_CLK	2999.970

Peripheral	Requested Frequency (MHz)	Source	Actual Frequency (MHz)
GEM1 freq (MHz)	125	IOPLL	124.998749
GEM2 freq (MHz)	125	IOPLL	124.998749
USB1 freq (MHz)	250	IOPLL	249.997498
QSPI freq (MHz)	300	IOPLL	299.997009
SDIO0 freq (MHz)	50	RPLL	48.484364
SDIO1 freq (MHz)	100	RPLL	96.968727
UART0 freq (MHz)	100	IOPLL	99.999001
UART1 freq (MHz)	100	IOPLL	99.999001
CPU_R5 freq (MHz)	533.333	RPLL	533.328003
IOU_SWITCH freq (MHz)	267	RPLL	266.664001
LPD_SWITCH freq (MHz)	533.333	RPLL	533.328003
LPD_LSBUS freq (MHz)	100	IOPLL	99.999001
NAND freq (MHz)	100	IOPLL	99.999001
GEM_TSU freq (MHz)	250	IOPLL	249.997498
TIMESTAMP freq (MHz)	100	PSS_REF_CLK	33.333000
PSU__CRL_APB__USB3_REF_CTRL__freqmhz	20	IOPLL	19.999800
PCAP freq (MHz)	200	IOPLL	187.498123
DBG_LPD freq (MHz)	250	IOPLL	249.997498
ADMA freq (MHz)	533.333	RPLL	533.328003
PL0 freq (MHz)	50	IOPLL	49.999500
AMS freq (MHz)	50	IOPLL	49.999500
ACPU freq (MHz)	1333.333	APLL	1333.320068
DBG FPD freq (MHz)	250	IOPLL	249.997498
DDR_CTRL freq MHz)	533.500	DPLL	533.328003
GPU freq (MHz)	600	IOPLL	499.994995
GDMA freq (MHz)	600	DPLL	533.328003
DPDMA freq (MHz)	600	DPLL	533.328003
TOPSW_MAIN freq (MHz)	533.333	DPLL	533.328003
TOPSW_LSBUS freq (MHz)	100	IOPLL	99.999001
DBG TSTMP freq (MHz)	250	IOPLL	249.997498

DDR Memory information

Parameter name	Value	Description
ENABLE	1	Enable the PS DDR Controller
DDR Interface freq (MHz)	1067	--
MEMORY TYPE	DDR 4	Type of memory interface
DM DBI	UDIMM
BUS WIDTH	64 Bit	Data width of DDR interface, not including ECC data width
ECC	Disabled	Enables error correction code support
SPEED BIN	DDR4_2133P	Speed Bin
CL	15	Column Access Strobe (CAS) latency in memory clock cycles. It refers to the amount of time it takes for data to appear on the pins of the memory module
CWL	14	CAS write latency setting in memory clock cycles
DDR AL	0	Additive Latency (ns). Increases the efficiency of the command and data bus for sustainable bandwidths
T RCD	15	tRCD. Row address to column address delay time. It is the time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS)
T RP	15	Precharge Time is the number of clock cycles needed to terminate access to an open row of memory and open access to the next row
T RC	46.5	Row cycle time (ns)
T RAS MIN	33	Minimum number of memory clock cycles required between an Active and Precharge command
T FAW	30.0	Determines the number of activates that can be performed within a certain window of time
DRAM WIDTH	8 Bits	Width of individual DRAM components
DEVICE CAPACITY	8192 MBits	Storage capacity of individual DRAM components
BG ADDR COUNT	2	Number of bank group address pins
RANK ADDR COUNT	0	Dual-rank or dual-DIMM configuration of DRAM. Addressed using two chip-select bits (CS_N)
BANK ADDR COUNT	2	Number of bank address pins
ROW ADDR COUNT	16	Number of row address pins
COL ADDR COUNT	10	Number of column address bits
C_DDR_RAM_HIGHADDR	0x1FFFFFFFF	--

GT lanes information

Protocol

GT lane#

Ref Clk Sel

Ref freq (MHz)